Model checking

Results: 996



#Item
841NuSMV / Invariant / Model checking

D-Finder: A Tool for Compositional Deadlock Detection and Verification Saddek Bensalem Marius Bozga

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Source URL: www-verimag.imag.fr

Language: English - Date: 2012-12-31 04:25:32
842Logic in computer science / Temporal logic / Model checkers / Formal methods / Model checking / Formal verification / Linear temporal logic / Computation tree logic / CTL* / Theoretical computer science / Mathematical logic / Applied mathematics

ACM 2007 Turing Award Edmund Clarke, Allen Emerson, and Joseph Sifakis Model Checking: Algorithmic Verification and Debugging ACM Turing Award Citation In 1981, Edmund M. Clarke and E. Allen Emerson, working in the USA,

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Source URL: www-verimag.imag.fr

Language: English - Date: 2012-12-31 04:25:30
843Turing Award laureates / Formal methods / Joseph Sifakis / Cybernetics / Systems theory / Component-based software engineering / Model checking / Turing Award / Amir Pnueli / Computer science / Science / Software engineering

2 A Dialogue with Professor Joseph Sifakis about Concurrent Systems Specification and Verification Professor Joseph Sifakis, http://www-verimag.imag.fr/~sifakis, is a

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Source URL: www-verimag.imag.fr

Language: English - Date: 2012-12-31 04:25:30
844Computing / Science / Object-oriented programming / Component-based software engineering / Modeling language / Binding immunoglobulin protein / Model checking / Actor model / Software design / Scientific modeling / Software engineering / Systems science

www.computer.org/software Rigorous Component-Based System Design Using the BIP Framework Anandu Basu, Saddek Bensalem, Marius Bozga, Jacques Combaz, Mohamad Jaber, Thanh-Hung Nguyen, and Joseph Sifakis

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Source URL: www-verimag.imag.fr

Language: English - Date: 2012-12-31 04:25:30
845Schedule / Computer science / Information / Data / Concurrency / Diagrams / Petri net

Priority Scheduling of Distributed Systems Based on Model Checking Ananda Basu1 , Saddek Bensalem1 , Doron Peled2 , and Joseph Sifakis1 1 2

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Source URL: www-verimag.imag.fr

Language: English - Date: 2012-12-31 04:25:32
846Models of computation / Model checkers / Esterel / Automata theory / Model checking / SIGNAL / Theoretical computer science / Uppaal Model Checker / Computing / Hardware description languages / Synchronous programming languages / Software engineering

✲ Towards Validated Real-Time Software✲ Valérie BERTIN†, Michel POIZE, Jacques PULOU

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Source URL: www-verimag.imag.fr

Language: English - Date: 2012-12-31 04:25:30
847Model checking / Software engineering / Embedded system / Real-time computing / Computing / Electronics / Esterel Technologies / SIGNAL / Hardware description languages / Synchronous programming languages / Esterel

TAXYS : a Tool for the Development and Verification of Real-Time Embedded Systems⋆ Etienne CLOSSE1 , Michel POIZE1 , Jacques PULOU1 , Joseph SIFAKIS2 , Patrick VENIER1 , Daniel Weil1 , and Sergio YOVINE2 1

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Source URL: www-verimag.imag.fr

Language: English - Date: 2012-12-31 04:25:31
848Science / Modeling language / Model checking / Enterprise modelling / Scientific modeling / Systems engineering

Aucun titre de diapositive

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Source URL: www-verimag.imag.fr

Language: English - Date: 2012-12-31 04:25:30
849Monetary economics / Monetary policy / Inflation / Demand for money / Money supply / New Keynesian economics / Keynesian economics / Monetary inflation / Central bank / Economics / Macroeconomics / Economic theories

Money in monetary policy design: Monetary cross-checking in the New-Keynesian Model

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Source URL: www.ecb.europa.eu

Language: English - Date: 2010-05-20 08:55:44
850Computer science / Grid computing / Mobile Transaction Models / Software engineering / Support / Model checking

S. Ramesh Professor Dept. of Computer Science and Engineering Indian Institute of Technology Bombay Ph: +[removed]7722 Fax: +[removed]0196

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Source URL: www.cse.iitb.ac.in

Language: English - Date: 2004-11-13 02:10:47
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